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SY58610U
3.2Gbps Precision, LVPECL 2:1 MUX with Internal Termination and Fail Safe Input
General Description
The SY58610U is a 2.5/3.3V, high-speed, fully differential LVPECL 2:1 MUX capable of processing clock signals up to 2.5GHz and data patterns up to 3.2Gbps. The SY58610U is optimized to provide a buffered output of the selected input with less than 10pspp total jitter. The differential input includes Micrel's unique, 3-pin input termination architecture that interfaces to LVPECL, LVDS or CML differential signals, (AC- or DC-coupled) as small as 100mV (200mVPP) without any level-shifting or termination resistor networks in the signal path. For AC-coupled input interface applications, an integrated reference voltage (VREF-AC) is provided to bias the VT pin. The outputs are 800mV LVPECL, with extremely fast rise/fall times guaranteed to be less than 130ps. The SY58610U operates from a 2.5V 5% supply or 3.3V 10% supply and is guaranteed over the full industrial temperature range (-40C to +85C). For applications that require CML or LVDS outputs, consider Micrel's SY58609U and SY58611U, 2:1 MUX with 400mV and 325mV output swings, respectively. The SY58610U is part of Micrel's high-speed, Precision Edge(R) product line. Datasheets and support documentation can be found on Micrel's web site at: www.micrel.com. Precision Edge(R)
Features
* Precision 800mV LVPECL 2:1 MUX * Guaranteed AC performance over temperature and voltage: - DC-to > 3.2Gbps throughput - <370ps propagation delay (IN-to-Q) - <130ps rise/fall times * Fail Safe Input - Prevents outputs from oscillating when input is invalid * Ultra-low jitter design - <1psRMS cycle-to-cycle jitter - <10psPP total jitter - <1psRMS random jitter - <10psPP deterministic jitter * High-speed LVPECL outputs * 2.5V 5% or 3.3V 10% power supply operation * Industrial temperature range: -40C to +85C * Available in 16-pin (3mm x 3mm) MLF(R) package
Applications
* * * * All SONET clock distribution Fibre Channel clock and data distribution Gigabit Ethernet clock and data distribution Backplane distribution.
Functional Block Diagram
Markets
* * * * * Storage ATE Test and measurement Enterprise networking equipment High-end servers
Precision Edge is a registered trademark of Micrel, Inc. MLF and MicroLeadFrame are registered trademarks of Amkor Technology. Micrel Inc. * 2180 Fortune Drive * San Jose, CA 95131 * USA * tel +1 (408) 944-0800 * fax + 1 (408) 474-1000 * http://www.micrel.com
November 2006
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SY58610U
Ordering Information(1)
Part Number SY58610UMG SY58610UMGTR(2)
Notes: 1. Contact factory for die availability. Dice are guaranteed at TA = 25C, DC Electricals only. 2. Tape and Reel.
Package Type MLF-16 MLF-16
Operating Range Industrial Industrial
Package Marking 610U with Pb-Free bar-line indicator 610U with Pb-Free bar-line indicator
Lead Finish NiPdAu Pb-Free NiPdAu Pb-Free
Pin Configuration
Truth Table
SEL 0 1 Output IN0 Selected IN1 Selected
16-Pin MLF(R) (MLF-16)
Pin Description
Pin Number 1, 4 Pin Name VT0, VT1 Pin Function Input Termination Center-Tap: Each side of the differential input pair terminates to the VT pin. This pin provides a center-tap to a termination network for maximum interface flexibility. See "Input Interface Applications" subsection. Reference Voltage: These outputs bias to VCC-1.2V. They are used for AC-coupling inputs IN and /IN. Connect VREF-AC directly to the corresponding VT pin. Bypass with 0.01F low ESR capacitor to VCC. Due to limited drive capability, the VREF-AC pin is only intended to drive its respective VT pin. Maximum sink/source current is 0.5mA. See "Input Interface Applications" subsection. Differential Inputs: These input pairs are the differential signal inputs to the device. Inputs accept DC-Coupled differential signals as small as 100mV (200mVpp). Each pin of the pairs internally terminates with 50 to the corresponding VT pin. If the input swing falls below a certain threshold (typical 30mV), the Fail Safe Input (FSI) feature will guarantee a stable output by latching the output to its last valid state. See "Input Interface Applications" subsection. Single-Ended Input: This single-ended TTL/CMOS-compatible input selects the inputs to the multiplexer. Note that this input is internally connected to a 25k pull-up resistor and will default to logic HIGH state if left open. The input-switching threshold is VCC/2. Positive Power Supply: Bypass with 0.1uF//0.01uF low ESR capacitors as close to the VCC pins as possible. LVPECL Differential Output Pair: Differential buffered output copy of the selected input signal. The output swing is typically 800mV. Unused output pair may be left floating with no impact on jitter. See "LVPECL Output Termination" subsection. Ground. Exposed pad must be connected to a ground plane that is the same potential as the ground pins. No connect.
2, 3
VREF-AC0, VREF-AC1
5, 6 15, 16
IN1, /IN1 IN0, /IN0
7
SEL
8, 13 9, 12
VCC /Q, Q
10, 11 14
GND, Exposed Pad NC
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SY58610U
Absolute Maximum Ratings(1)
Supply Voltage (VCC) ............................... -0.5V to +4.0V Input Voltage (VIN) .......................................-0.5V to VCC LVPECL Output Current(IOUT) Continuous.......................................................50mA Surge .............................................................100mA Current (VT) Source or sink on VT pin .............................100mA Input Current Source or sink Current on (IN, /IN) ................50mA Current (VREF) Source or sink current on VREF-AC(4) ..............0.5mA Maximum operating Junction Temperature ......... 125C Lead Temperature (soldering, 20sec.) .................. 260C Storage Temperature (Ts) ....................-65C to +150C
Operating Ratings(2)
Supply Voltage (VIN)........................ +2.375V to +3.60V Ambient Temperature (TA) ................... -40C to +85C Package Thermal Resistance(3) MLF(R) Still-air (JA) ............................................ 60C/W Junction-to-board (JB) ......................... 33C/W
DC Electrical Characteristics(5)
TA = -40C to +85C, unless otherwise stated.
Symbol VCC ICC RDIFF_IN VIH VIL VIN VDIFF_IN VIN_FSI VREF-AC VT_IN
Notes: 1. Permanent device damage may occur if absolute maximum ratings are exceeded. This is a stress rating only and functional operation is not implied at conditions other than those detailed in the operational sections of this data sheet. Exposure to absolute maximum ratings conditions for extended periods may affect device reliability. 2. The data sheet limits are not guaranteed if the device is operated beyond the operating ratings. 3. Package thermal resistance assumes exposed pad is soldered (or equivalent) to the device's most negative potential on the PCB. JB and JA values are determined for a 4-layer board in still-air number, unless otherwise stated. 4. Due to the limited drive capability, use for input of the same package only. 5. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established. 6. VIN (max) is specified when VT is floating.
Parameter Power Supply Voltage Range Power Supply Current Differential Input Resistance (IN-to-/IN) Input HIGH Voltage (IN, /IN) Input LOW Voltage (IN, /IN) Input Voltage Swing (IN, /IN) Differential Input Voltage Swing (|IN - /IN|) Input Voltage Threshold that Triggers FSI AC Reference Voltage Voltage from Input to VT
Condition
Min 2.375 3.0
Typ 2.5 3.3 40
Max 2.625 3.6 50 110 VCC VIH-0.1 1.0
Units V mA V V V V
No load, max. VCC 90 IN, /IN IN, /IN see Figure 3a, Note 6 see Figure 3b 1.2 0.2 0.1 0.2
100
30 VCC-1.3
100 VCC-1.0 1.28
mV V V
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SY58610U
LVPECL Outputs DC Electrical Characteristics(7)
VCC = +2.5V 5% or +3.3V 10%, RL = 50 to VCC-2V; TA = -40C to +85C, unless otherwise stated.
Symbol VOH VOL VOUT VDIFF_OUT Parameter Output HIGH Voltage Output LOW Voltage Output Voltage Swing Differential Output Voltage Swing Condition Q0, /Q0, Q1, /Q1 Q0, /Q0, Q1, /Q1 See Figure 3a See Figure 3b Min VCC-1.145 VCC-1.945 550 1100 800 1600 Typ Max VCC -0.895 VCC-1.695 950 Units V V mV mV
LVTTL/CMOS DC Electrical Characteristics(70)
VCC = 2.5V 5% or 3.3V 10%; TA = -40C to + 85C, unless otherwise stated.
Symbol VIH VIL IIH IIL
Notes: 7. The circuit is designed to meet the DC specifications shown in the above table after thermal equilibrium has been established.
Parameter Input HIGH Voltage Input LOW Voltage Input HIGH Current Input LOW Current
Condition
Min 2.0
Typ
Max 0.8
Units V V A A
-125 -300
30
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SY58610U
AC Electrical Characteristics(8)
VCC = +2.5V 5% or +3.3V 10%, RL = 50 to VCC-2V; Input tR/tF < 300ps, TA = -40C to +85C, unless otherwise stated.
Symbol fMAX tPD Parameter Maximum Frequency Propagation Delay SEL-to-Q tSkew tJitter Input-to-Input Skew Part-to-Part Skew Data Clock tR, tF Random Jitter Deterministic Jitter Cycle-to-Cycle Jitter Total Jitter Output Rise/Fall Times (20% to 80%) Duty Cycle
Notes: 8. 9 10 High-frequency AC-parameters are guaranteed by design and characterization. Input-to-input skew is the time difference between the two inputs to one output, under identical input transitions. Input-to-Input Skew is included in IN-to-Q propagation delay.
Condition NRZ Data VOUT > 400mV IN-to-Q VIN: 100mV-200mV VIN: >200mV Note 9, 10 Note 11 Note 12 Note 13 Note 14 Note 15 At full output swing. Differential I/O Clock
Min 3.2 2.5 180 140 150
Typ 3 340 290 5
Max
Units Gbps GHz
470 370 450 20 150 1 10 1 10
ps ps ps ps ps psRMS psPP psRMS psPP ps %
40 47
100
130 53
11. Part-to-part skew is defined for two parts with identical power supply voltages at the same temperature, same transition edge, and no skew at the edges at the respective inputs. 12. Random jitter is measured with a K28.7 pattern, measured at fMAX. 13. Deterministic jitter is measured at 2.5Gbps with both K28.5 and 2 -1 PRBS pattern. 14. Cycle-to-cycle jitter definition: the variation period between adjacent cycles over a random sample of adjacent cycle pairs. tJITTER_CC = Tn -Tn+1, where T is the time between rising edges of the output signal. 15. Total jitter definition: with an ideal clock input frequency of fMAX (device), no more than one output edge in 10^12 output edges will deviate by more than the specified peak-to-peak jitter value.
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SY58610U
Functional Description
Fail-Safe Input (FSI) The input includes a special fail-safe circuit to sense the amplitude of the input signal and to latch the outputs when there is no input signal present, or when the amplitude of the input signal drops sufficiently below 100mVPK (200mVPP), typically 30mVPK. Maximum frequency of the SY58610U is limited by the FSI function.
Input Clock Failure Case If the input clock fails to a floating, static, or extremely low signal swing, such that the voltage swing across the input pair is less than 100mV, the FSI function will eliminate a metastable condition and latch the outputs to the last valid state. No ringing and no undetermined state will occur at the output under these conditions. The output recovers to normal operation once the input signal returns to a valid state with a swing greater than 100mV. Note that the FSI function will not prevent duty cycle distortion in case of a slowly deteriorating (but still toggling) input signal. Due to the FSI function, the propagation delay will depend on rise and fall time of the input signal and on its amplitude. Refer to "Typical Operating Characteristics" for detailed information.
Timing Diagrams
Figure 1a. Fail Safe Feature
Figure 1b. Propagation Delay IN-to-Q
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SY58610U
Figure 1c. Propagation Delay SEL-to-Q
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SY58610U
Typical Characteristics
VCC = 3.3V, GND = 0V, VIN = 100mV, RL = 50 to VCC-2V, TA = 25C, unless otherwise stated.
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SY58610U
Functional Characteristics
VCC = 3.3V, GND = 0V, VIN = 400mV, RL = 50 to VCC-2V, TA = 25C, unless otherwise stated.
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SY58610U
Functional Characteristics (continued)
VCC = 3.3V, GND = 0V, VIN = 400mV, RL = 50 to VCC-2V, TA = 25C, unless otherwise stated.
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SY58610U
Input and Output Stage
Single-Ended and Differential Swings
Figure 3a. Single-Ended Voltage Swing
Figure 2a. Simplified Differential Input Buffer Figure 3b. Differential Voltage Swing
Figure 2b. Simplified LVPECL Output Buffer
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SY58610U
Input Interface Applications
Figure 4a. CML Interface (DC-Coupled)
Option: May connect VT to VCC
Figure 4b. CML Interface (AC-Coupled)
Figure 4c. LVPECL Interface (DC-Coupled)
Figure 4d. LVPECL Interface (AC-Coupled)
Figure 4e. LVDS Interface
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SY58610U
LVPECL Output Termination
LVPECL output has very low output impedance (open emitter), and small signal swing which results in low EMI. LVPECL is ideal for driving 50 and 100controlled impedance transmission lines. There are several techniques in terminating the LVPECL output, as shown in Figures 5a and 5b.
Figure 5b. Three-Resistor "Y-Termination"
Figure 5a. Parallel Termination-Thevenin Equivalent
Related Product and Support Documents
Part Number SY58609U SY58611U HBW Solutions Function 4.25Gbps Precision, CML 2:1 MUX with Internal Termination and Fail Safe Input 3.2Gbps Precision, LVDS 2:1 MUX with Internal Termination and Fail Safe Input New Products and Termination Application Notes Data Sheet Link http://www.micrel.com/_PDF/HBW/sy58609u.pdf http://www.micrel.com/_PDF/HBW/sy58611u.pdf http://www.micrel.com/page.do?page=/productinfo/as/HBWsolutions.shtml
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Micrel, Inc.
SY58610U
Package Information
16-Pin (3mm x 3mm) MLF(R) (MLF-16)
MICREL, INC. 2180 FORTUNE DRIVE SAN JOSE, CA 95131 USA
TEL +1 (408) 944-0800 FAX +1 (408) 474-1000 WEB http:/www.micrel.com
The information furnished by Micrel in this data sheet is believed to be accurate and reliable. However, no responsibility is assumed by Micrel for its use. Micrel reserves the right to change circuitry and specifications at any time without notification to the customer. Micrel Products are not designed or authorized for use as components in life support appliances, devices or systems where malfunction of a product can reasonably be expected to result in personal injury. Life support devices or systems are devices or systems that (a) are intended for surgical implant into the body or (b) support or sustain life, and whose failure to perform can be reasonably expected to result in a significant injury to the user. A Purchaser's use or sale of Micrel Products for use in life support appliances, devices or systems is a Purchaser's own risk and Purchaser agrees to fully indemnify Micrel for any damages resulting from such use or sale. (c) 2006 Micrel, Incorporated.
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